1. Field of the Invention
This invention relates to computer memory. More particularly, it relates to constructing a memory unit having a given capacity from a plurality of partially good memory modules, where the location of the usable portion in each memory module is known.
2. Description of the Prior Art
The desire to use partially good memory modules has existed for some time in order to minimize the expense associated with scrapping defective modules. Traditional, conventional efforts to utilize partially defective memory modules have to do with alternate addressing schemes for avoiding the defective area. References illustrative of this aspect of the prior art include U.S. Pat. No. 3,845,476 to Boehm, commonly assigned, which uses address translation to avoid bad memory sections and teaches a method of making a monolithic memory. The reference requires that a combination of memory chips include at least one all-good chip and further teaches programmable means connected between the translation means and the chips for assuring that certain addressing signals correspond to the address of a defective chip sector irrespective of which one of the sectors in the partially defective chip is actually defective.
It is known in the art to predetermine the configuration of good memory capacity in a partially defective memory module. This feature is described with respect to memory chips in IBM Technical Disclosure Bulletin, Vol. 21, No. 9, Feb., 1979, p. 3582 to Meyers et al and commonly assigned U.S. Pat. No. 3,735,368 to W. F. Beausoleil.
Meyers et al sort memory chips which are partially defective into ten categories; eight, where seven-eighths of the memory chip is good and two, where the chip is half good. These chips are combined in a manner which results in a single unit part number, logically equivalent to a unit having four all good memory chips.
IBM Technical Disclosure Bulletin, Vol. 15, No. 11, April 1973, page 3453 to Chiriatti combines two types of half good memory chips to substitute for units containing all good memory chips of equal memory capacity without modifying the card on which the units are mounted and without requiring logic circuit transformation.
IBM Technical Disclosure Bulletin, Vol 1, No. 1, June, 1985, page 10 to Kruggel et al uses alterable steering devices to assure that good memory circuits are connected to certain identified I/O pads. Thus all chips having an equal number of good circuits are assigned a single part number regardless of possible difference in physical location of the failures.
This article discloses a capability of interchanging I/O connections between chip circuits and unit pins in a partially good chip. One of the data I/O circuits is designated as a replacement circuit for any other which might be found defective. A good circuit is connected to an I/O pad intended for the circuit found defective by means of fuse blowing or any of several laser methods.
Kruggel et al appear to require that partially good chips have the same number of defective sections, whereas the present invention contemplates a mixture of half, three-quarter and full or any combination thereof of good units to comprise a single memory SIMM.
Kruggel et al is similar, somewhat, to the present invention in they make all connections and then selectively break some whereas in the present invention we selectively make connections between data output lines from memory modules and output terminals on a substrate.
Because of the tremendous cost associated with high volume manufacturing operations, it is desirable to be able to use partially defective memory modules in constructing memory units of a given size or aggregate capacity. In the course of manufacturing memory modules, prediction of the configuration of defective bits in a given lot is difficult. Some defects occur at wafer level while others show up only after a module is built. Since it is difficult to predict precise, usable bit configurations available from a given wafer manufacturing run, even a slight shift in process parameters can result in vast differences in partially good bit configurations. Such partially defective modules are often scrapped.
It is possible to prepare in advance for all possible partially good bit configurations but such a situation requires maintaining on hand a very large number of substrates, each circuitized in predetermined wiring patterns to accommodate the various possible combinations of partially good modules.